The field of reconfigurable computing has advanced steadily for the past decade, using programmable logic devices (PLDs) as the basis for high-performance reconfigurable systems. Run-Time Reconfigurable (RTR) systems distinguish themselves by performing circuit logic customization at run-time. RTR systems using PLDs are expected to result in systems that require less hardware, less software, and fewer input/output resources than traditional ASIC or PLD-based systems.
In multiprocessor data processing systems, various systems are known for balancing the work load between the processors. An advantage to such systems is that the functions implemented by the system can be software controlled, thereby providing great flexibility. However, such systems tend to be large, expensive, and complex. Furthermore, software-implemented functions tend to be slower than hardware implementations.
A system and method that address the aforementioned problems, as well as other related problems, are therefore desirable.